1. Field of the Invention
The present invention relates to a method for producing a spiral inductance on a substrate and a device that is fabricated in accordance with such the method.
2. Description of the Background Art
With increasing operating frequency, device modeling for devices that are integrated on a semiconductor substrate is playing an increasingly bigger role because it causes transmission-line properties, reflections on discontinuities, overlapping and dissipations to increase. Thus, taking these effects into consideration in modeling, particularly in the high frequency field, is generally a must. In particular, in a low-resistance substrate, for example a silicon substrate of a silicon-germanium substrate, the parasitic influence of the substrate conductance and additional capacitances is not to be neglected.
Although generally applicable to any inductance, the present invention and the problems it is based on is described in detail in regard to a spiral inductance.
Inductances integrated on a substrate are valuable devices in radio frequency circuitries, which have a wide application range, for example, in cordless communication systems. Categorized as cordless communication systems are, for example, personal communication services, wireless local area networks, satellite communication systems, global positioning (GPS) systems, etc.
General problems with integrated inductances are the relative low quality factors, obtaining a satisfactory grounding, deviating characteristics depending on the substrate geometry, electromagnetic couplings between inductances and the substrate, and relatively low self-resonance frequencies. The inductances are often used as small band loads in radio frequency circuits, for example, amplifiers, oscillators, or the like. Thus, there is a wide field of application to be found for inductances, particularly in the consumer electronics market. However, production costs, integration density, and reliability are additional deciding factors, which have to be considered in the production of integrated inductances.
Since the technology in the radio frequency field is shifting from big systems with a wide transmission range to smaller systems with a more limited range, and newer systems are increasingly becoming mobile systems, the trend in the RF field is to build radio-frequency-suitable devices that are more economical and easier to use.
To realize integrated inductances, spiral inductances have become accepted in planar circuit technology. The attainable inductance values hereby range from 0.1 nH to 10 nH. The spiral inductances can thereby have round as well as rectangular windings with diverse geometries. Spiral inductances play an important role in, for example, integrated circuits in the radio frequency field, whereby they are frequently used as devices for minimizing phase noises, as inductances with low dissipation for LNA connections, or as inductances with low electrical resistance for amplifier outputs, as loads, or as emitters/source degenerators with negligible voltage drop for operations in the low voltage area in silicon-based integrated circuit processes.
The problem in general is, therefore, that an integration of planar spiral inductances on, for example, a silicon substrate, usually results in performance losses in regard to the resonance frequency and the quality factor. Primarily, the coupling between the spiral inductance and its surrounding area over the silicon substrate, and the lack of a good earth plane due to substrate losses is the cause of such disadvantages of the integrated spiral inductances. In addition, the magnetic flow along the coil, which is directed vertically into the substrate, also causes substrate losses due to the generated eddy currents. These effects also reduce the quality factor of the integrated planar spiral inductance.
Several conventional attempts have been made to integrate spiral inductances in a silicon substrate with the objective to improve the quality factor and the natural frequency resonance of the inductances on the silicon substrate.
In a conventional approach, the winding width of the windings of the spiral inductance is steadily increased from the inside to the outside, as is illustrated in FIG. 1. The magnetic losses of the spiral inductance can thereby be considerably reduced. However, this is relatively difficult to do.
FIG. 2 illustrates a further conventional approach, whereby in contrast to an inductance having only one end, two winding units are positioned in correlation to one another to raise the quality factor and the self-resonance frequency. The voltages and currents on the terminals A1 and A2 preferably have a phase offset of 180 degrees. However, this approach has the disadvantage that high coupling, that is, substrate losses occur.
FIG. 3 illustrates a further conventional approach for producing an integrated inductance, whereby a p-n-p transition vertical to the eddy current flow is utilized to reduce the substrate losses of the integrated inductance 6. The eddy currents are indicated in FIGS. 3 and 4 by closed, interconnected arrows.
FIG. 4 illustrates a further conventional approach, whereby a structured ground shielding between two adjacent inductances is used to raise the quality factor and to minimize the substrate coupling. The ground metallization is lamellar, with slots arranged in between, which are etched into the ground metallization 5 in a direction that is vertical to the spiral inductance. The width of the slots should be narrow enough to prevent the electrical field from penetrating the silicon substrate below. This, however, requires a relatively elaborate procedure.
FIG. 5 illustrates an inductance structure according to a further conventional approach. The wafer is hereby thinned from the bottom side of the silicon substrate in order to integrate the spiral coil space-economically on the wafer. The disadvantage thereby is that substantial substrate losses occur.
Lastly, FIG. 6 illustrates a further conventional approach to an integrated inductance. A back-etched area 19 in the substrate 1 below the windings 6 is thereby etched, whereby the windings 6 are supported over the back-etched area 19 by bridging metallizations 18. The back-etched area 19 reduces the electromagnetic coupling between the inductance 6 and the substrate 1 and reduces the parasitic capacitance between the inductance 6 and the silicon substrate 1, which results in a raised quality factor and self-resonance frequency. This back-etched area 19 is formed deep enough so that potentially induced eddy currents are reduced. Thus, the entire dissipation is substantially reduced.
The disadvantage of this conventional approach has proven to be the fact that the production process is very complicated, expensive, and time-consuming. Furthermore, a parasitic capacitance between the metallizations 6 and substrate 1 remains due to the bridging metallizations 18. In addition, the fabrication of this bridging construction requires method steps for forming the bridging construction, which include a reactive ionic etching (DRIE) and the deposition of an approximately 30 μm-thick silicon dioxide layer.